Silicon Labs /Series0 /EZR32HG /EZR32HG320F32R67 /DMA /STATUS

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Interpret as STATUS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EN)EN 0 (IDLE)STATE0CHNUM

STATE=IDLE

Description

DMA Status Registers

Fields

EN

DMA Enable Status

STATE

Control Current State

0 (IDLE): Idle

1 (RDCHCTRLDATA): Reading channel controller data

2 (RDSRCENDPTR): Reading source data end pointer

3 (RDDSTENDPTR): Reading destination data end pointer

4 (RDSRCDATA): Reading source data

5 (WRDSTDATA): Writing destination data

6 (WAITREQCLR): Waiting for DMA request to clear

7 (WRCHCTRLDATA): Writing channel controller data

8 (STALLED): Stalled

9 (DONE): Done

10 (PERSCATTRANS): Peripheral scatter-gather transition

CHNUM

Channel Number

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